Field
The present invention relates to a technique for electrically connecting a printed circuit board to a chip defining one or more electronic devices.
Background
One known technique of connecting a printed circuit board to a chip is known as wafer-level chip scale packaging (WLCSP), in which the “package” or interconnect elements are fabricated on the wafer prior to singulation. This technique is characterized in that: (a) there is no pre-assembly of the chip on a substrate before mounting onto the printed circuit board; and (b) the chip is ready for surface mounting on a printed circuit board as soon as it is singulated from the wafer. The area that the thus packaged chip occupies when mounted onto a printed circuit board is the size of the silicon die.
One such interconnection between a chip or integrated circuit 6 and a printed circuit board 2 is shown in FIG. 1, where the solder ball is designated by reference numeral 4. Also shown in FIG. 1 are the common locations 5 where cracks have been found to develop when the assembly is subject to impact testing, such as drop testing.